1. Field of the Invention
The present invention relates generally to the field of microelectronics. More particularly, the present invention is directed to a system and method for controlled parameter re-centering in a controlled phase lock loop system.
2. Background
As the drive toward system-on-chip (SOC) integration continues, higher percentages of integrated circuit (IC) designs contain one or more current-controlled or voltage-controlled phase locked loops (PLLs) that provide a number of functions, including clock phase alignment, clock frequency synthesis, delay cell reference generation and communications transmit and recovery functions, among others. While such controlled loops may be built using any number of device and topology types, they generally rely on the relationship between a small number of oscillating circuits within the loop and an oscillation control parameter, such as current or voltage, to dynamically tune the oscillating circuit to a desired reference frequency. Simulation of current-controlled oscillator (ICO) and voltage-controlled oscillator (VCO) structures reveals that, in most cases, the design points of these structures seek to utilize a linear, or near-linear, portion of the control parameter (e.g., current or voltage) versus frequency response curve in order to provide the highest level of control over the oscillating loop structure.
In addition, in designing controlled loop structures, designers must consider the inherent performance shifts of the oscillating structures that may vary up to 300% relative to design values over the process, temperature and voltage (PVT) range of circuit/system. Designers must also consider in finalizing a design that the tuning range of the controlled loop can vary, e.g., from less than 5 MHz for a recovery system to greater than 500 MHz for a synthesis system. While controlled loop designs having relatively low oscillator gains (e.g., MHz/V or MHz/mA) are typically preferred due to their improved jitter performance and lower loop bandwidths, such designs are often not possible when tuning ranges are broadened but the range of control voltage or current remains fixed. This makes designing general PLLs more difficult.
FIG. 1 illustrates a performance envelope 10 for a hypothetical PLL having a relatively low oscillator gain and a relatively narrow tuning bandwidth. For this hypothetical PLL, the normal operating voltage ranges from 0.9 volts to 1.1 volts, i.e., 0.1 volts to either side of a center voltage of 1.0 volts. Among other things, FIG. 1 indicates that this hypothetical PLL has a maximum tuning range 14 of about 400 MHz to about 540 MHz over the voltage range of 0.9 volts to 1.1 volts considering not only the nominal gain curve 10a but the best case gain curve 10b and worst case gain curve 10c which are derived considering PVT variations from the design point. To maximize product yield and ensure function across its specified range, the PLL must be able to achieve its target frequencies 18 within the allowed control parameter (voltage) range 20 across the entire performance envelope 10. Consequently, if a particular SOC design required a PLL having target frequencies 18 of 470 MHz, 650 MHz and 710 MHz, the PLL having performance envelope 10 of FIG. 1 would not be satisfactory since it could not provide the 650 MHz and 710 MHz target frequencies under normal voltage conditions since the oscillator gain is relatively low ([540 MHz−400 MHz]/[1.1 V−0.9 V]=700 MHz/V).
FIG. 2 illustrates a performance envelope 22 along with the nominal design point 22a, the best case PVT bounds 22b and the worst case PVT bounds 22c for a second hypothetical PLL having a relatively high oscillator gain and a relatively wide tuning bandwidth. As FIG. 2 shows, if it is desired to have a PLL capable of providing the three target frequencies 18 noted above, i.e., of 470 MHz, 650 MHz and 710 MHz, the oscillator having the performance envelope of FIG. 2 would satisfy this need since its tuning range 26 is on the order of 400 MHz to 800 MHz for the normal control parameter (voltage) range 20 of 0.9 V to 1.1 V, thereby encompassing the three target frequencies 18. However, this relatively large tuning range 26 is achieved with an undesirably high gain ([800 MHz−400 MHz]/[1.1 V−0.9 V]=2000 MHz/V), which can lead to difficulties with jitter and control loop stability.
Compounding the difficulties that relatively large required tuning ranges pose is the trend toward lower operating voltages with each new generation of semiconductor technology. These lower operating voltages negatively impact the linear, or nearly so, portion of the frequency response curve, while not significantly impacting the best-to-worst case range of performance of circuit elements under allowed PVT range. Presently, the static PVT operating point ranges consume a majority of the linear portion of a PLL's response curve, leaving little room for accommodating the relatively large frequency ranges desired and while posing risks to circuit functionality and yields